This invention pertains to an electrical interconnection device, and more particularly to such a device for electrically interconnecting individual layers of a multilayer microelectronic structure with each other and with other electrical devices.
The present invention is addressed to the interconnection difficulties created when integrated circuits or other microelectronic structures are stacked or layered together, such a structure being termed in this application as a stratolith. The present invention provides a unique interconnection with the multilayered structure using a specially fabricated monolithic integrated circuit device.
By way of example, in applicant's U.S. Pat. No. 4,506,387 a Programming-On-Demand Cable System is described which makes it desirable to incorporate as much computer-type memory as possible in the limited volume of a home entertainment consumer device, such as a television. The minimum memory capacity desired is forty billion bytes. If such a memory were constructed from existing discrete devices, such as a 256 kilobit RAM or bubble memory module, as many as 1,220,704 units would be needed, enough to fill a large room.
A typical 256 kilobit memory chip has a memory density of 32 kilobytes per 25 mm.sup.2, or, in other words, 128 kilobytes per cm.sup.2. Using wafer scale integration and stratolithic technology to create a stack of double-sided wafers 200 microns thick, the memory density would be 13,107,200 bytes per cm.sup.3. Forty billion bytes would therefore require about 3,052 cm.sup.3. This is approximated by a cube 15 centimeters on each side, a much more manageable size.
One problem that must be addressed before chips can be stacked in such a stratolith is that of interconnection between individual layers and external devices. When chips are only fifty microns thick, it is virtually impossible, using any prior art technique known to the applicant, to make specific connections to chips stacked as described above. The present invention accomplishes such connections by applying integrated circuit technology to fabricate what are essentially microscopic connections, in keeping with the microscopic thicknesses of the chips.